Time-Based Analog-to-Digital Converter (ADC), at scaled CMOS technology, plays a major role in designing Software Defined Radio (SDR) receivers as it manifests higher speed and lower power than conventional ADCs. Time-Based ADC includes a Voltage-to-Time Converter (VTC) or a Voltage-Controlled Delay Unit (VCDU) which converts the input voltage into a pulse delay, and a Time-to-Digital Converter (TDC) which converts the pulse delay into a digital word. In this paper, we present two novel differential VTCs fabricated using TSMC 65nm CMOS technology with ideal TDCs and no sample-and-hold circuit producing complete ADCs.
The first proposed ADC is based on the design of a VCDU. This new ADC operates on a higher sampling frequency of 8 Gsample/sec, with a supply voltage of 1-V. It achieves a wider dynamic-range of 560 mV and a 3% linearity error. Simulation results reveal that this design can achieve up to a 9-bit resolution with Effective Number of Bits (ENOB) of 8.9902 bits in an 8-GHz bandwidth and a 0.3918 fJ/conversion FOM. It consumes a 1.594 mW power. The second proposed ADC is based on a new design methodology which reports a wider dynamic range of 1 V and a higher sensitivity of 9.6 рs/mV. This new ADC operates on a 2.5 Gsample/sec sampling frequency with a 3% linearity error and with a supply voltage of 1.2 V. It also achieves a resolution up to 11 bits with ENOB of 10.7228 bits in a 2.5-GHz bandwidth and a 0.03763 fJ/conversion FOM. It consumes a 0.159 mW power.
This article is published in peer review journal and open access journal, International journal of research in engineering and innovation (IJREI) which have a high impact factor journal for more details regarding this article, please go through our journal website.
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